1. Field of the Invention
The present invention relates to a phase-locked loop circuit (hereinafter, referred to as PPL circuit) and, particularly, it relates to a PPL circuit having a phase comparator which is arranged to compare two incoming pulse signals and to produce an output signal, only during a time of predetermined length in every period of one of said two pulse signals, said output signal being at a level varying in accordance with a level of the other of said pulse signals.
2. Description of the Related Art
The prior art will be described with reference to FIG. 5, which is a block diagram of the conventional PLL circuit of this kind.
The circuit shown in FIG. 5 includes a synchronizing separator circuit 1 for separating a synchronizing signal out of an incoming signal, a phase comparator 2 arranged to compare two incoming signals and to produce an output voltage which varies, during a time when one of the two incoming signals is at L (low) level, according to high or low level of the other of said two incoming signals, a low pass filter and phase compensating filter 3 (hereinafter referred to as LPF/PCF), an amplifier 4 (hereinafter referred to as AMP), a voltage-controlled oscillator 5 (hereinafter referred to as VCO) having an output frequency which varies according to an output voltage of said AMP 4, and a frequency divider 6 arranged to effect 1/n frequency division of the output of said VCO 5.
FIG. 6 is a timing chart showing wave forms of signals at several parts in FIG. 5.
FIG. 6 A2 illustrate the wave forms generated when the PLL circuit shown in FIG. 5 operates in normal manner and B2 and C2 illustrate the wave forms generated when the PLL circuit operates in undesirable manner.
Referring to FIG. 5, it is now assumed that a video signal, for example a NTSC signal, is fed to the synchronizing separator circuit 1. The circuit 1 operates to separate a horizontal synchronizing signal and to feed a signal (a) to the phase comparator 2. The signal (a) becomes at L (low) level for a predetermined time, in synchronized relationship with a drop-off of the horizontal synchronizing signal, as shown in FIG. 6. The phase comparator, which received the signal (a), produces an output voltage signal (c), which becomes lower during a period when another incoming signal (b) is at H (high) level while said signal (a) is at L level and which becomes higher during a period when said another incoming signal (b) is at L level while the signal (a) is at L level. Depending upon these signals (a) and (b), the phase comparator 2 produces the output signal (c) having the wave form as shown in FIG. 6 A2. The signal (c) is transmitted through the LPF/PCF 3 and AMP 4 to the VCO 5, which is driven thereby. An output signal of the VCO 5 is frequency-divided to 1/n by the frequency divider 6 and an output of this frequency divider forms the other incoming signal of the phase comparator 2, as mentioned above.
The above-described PLL circuit per se forms a subject of a co-pending U.S. patent application Ser. No. 659,717, which was field on Oct. 11, 1984 and assigned to the assignee of the present invention. Such application issued on Dec. 2, 1986 as U.S. Pat. No. 4,626,797.
According to the construction of the PLL circuit as described above, the phase comparator 2 may produce an output of undesirable wave form at the time of closing a power source switch. The wave form as shown by (c) in FIG. 6 B2 may be generated when the output frequency of the frequency divider 6 is small, while the wave form as shown in (c) of FIG. 6 C2 may be generated when the output frequency of the frequency divider 6 is large. When such wave forms are generated, the PLL circuit becomes stable and thus it becomes in locked state under the undesirable state as shown in FIG. 6 B2 or FIG. 6 C2. That is, the PLL circuit is at a false or pseudo stable state. Such a false or pseudo stable state, of course, adversely affects a precision of synchronization of the PLL circuit.